Memory devices conventionally include arrays of bit cells that each store a bit of data. Each data bit can represent a logical zero (“0”) or a logical one (“1”), which may correspond to a state of the bit cell. During a read operation of a selected bit cell, a voltage level close to ground may be representative of “0” and a relatively higher voltage level may be representative of “1”. Bit lines are coupled to various bit cells in the memory array and the bit lines couple the bit cells to other components used in read/write operations.
Magnetoresistive random access memory (MRAM) is a non-volatile memory technology where data is stored based on magnetization polarities of bit cells. In contrast to conventional RAM technologies that store data as electric charges or current flows, MRAM uses magnetic elements. A magnetic tunnel junction (MTJ), which is conventionally used as a storage element or bit cell for MRAM technology, can be formed from two magnetic layers, each of which can hold a magnetic moment, separated by an insulating (tunnel barrier) layer. Conventionally, the fixed layer is set to a particular polarity. The free layer's polarity is free to change to match that of an external magnetic field that can be applied. A change in the polarity of the free layer will change the resistance of the MTJ bit cell. For example, when the magnetization polarities are aligned or “parallel,” a low resistance state (RL) exists, which corresponds to a logical “0”. When the magnetization polarities are not aligned or are “anti-parallel,” a high resistance state (RH) exists, which corresponds to a logical “1”.
Thus, in magnetoresistive random access memory (MRAM), each bit cell (e.g., a MTJ bit cell) has a resistance value based on whether the bit cell represents a logical zero (“0”) or a logical one (“1”). Specifically, the resistance of the bit cell (Rdata) relates to the data stored in the bit cell.
Thus, in order to write a logical “0” or a logical “1,” corresponding write currents are passed through the MTJ bit cell to effect a corresponding alignment of the free layer and the fixed layer, or in other words to program the MTJ bit cell to the corresponding resistance state.
In order to read the bit cell, a sensing current is passed through the bit cell and a voltage Vdata developed across the resistance Rdata is then compared to a reference voltage Vref. If Vdata is high relative to Vref, then the bit cell is determined to have a logical “1” stored therein. If Vdata is low relative to Vref, then the bit cell is determined to have a logical “0” stored therein. The difference between the voltage across the bit cell Vdata and the reference voltage Vref, (differential voltage ΔV=Vdata−Vref) is therefore used to indicate the logic state stored in the bit cell. A sensing margin refers generally refers to the amount by which ΔV must be correctly sensed as positive or negative in order to correctly read the value stored in the bit cell as “1” or “0” respectively.
In general, the output voltage difference ΔV (=Vdata−Vref) in the sensing circuit is determined by the sensing current difference ΔI (=Iref−Idata) and output resistance of load PMOS (rO_PLD): ΔV=ΔI*rO_PLD.
For example, when the MTJ is state 0 (Rdata=RL):
Idata>Iref since RL<Rref;
Vdata<Vref; and
ΔV (=Vdata−Vref) becomes negative.
When the MTJ is state 1 (Rdata=RH):
Idata<Iref since RH>Rref;
Vdata>Vref; and
ΔV (=Vdata−Vref) becomes positive.
In conventional sense amplifiers, however, the sensing margin is degraded with technology scaling due to a decrease in supply voltage, an increase in process variation, and limited sensing current to prevent read disturbances. To combat these problems, designers have turned to tighter magnetic tunnel junction (MTJ) resistance (RL and RH) distributions or novel bit-cell structures (e.g., separated read and write paths). Unfortunately, these solutions have their own problems, such as poor sensing margins and slow speeds along with issues in manufacturing process variations that result in widely varying performance of the circuits. In general, the degradation in the sensing margin is overcome by using offset tolerant sensing circuits. However, these circuits have inherent performance degradation because of the use of a multi-stage sensing operation.
FIG. 1A illustrates a conventional sensing circuit. To consider offset effect in the sensing circuit, following terminologies are defined:
Vdata_ideal: Vdata in case of no process variation in the sensing circuit;
Vref_ideal: Vref in case of no process variation in the sensing circuit;
VSC_OS1: offset voltage caused by the process variation in the left branch of sensing circuit;
VSC_OS2: offset voltage caused by the process variation in the right branch of sensing circuit;
Vdata=Vdata_ideal+VSC_OS1;
Vref=Vref_ideal+VSC_OS2; and
ΔVideal=|Vdata_ideal−Vref_ideal|.
FIG. 1B illustrates the two stages of operation for a conventional offset tolerant sensing circuit, such as that shown in FIG. 1A. As shown in FIG. 1B,
When Rdata=RL:
VSA_data=Vdata_1st_ideal+VSC_OS1;
VSA_REF=Vref_2nd_ideal+VSC_OS1;
VSA_data VSA_REF=−2ΔVideal;
where Vdata_1st_ideal;
=(Vdata0_ideal+Vdata1_ideal)/2−ΔVideal;
Vref_2nd_ideal; and
=(Vdata0_ideal+Vdata1_ideal)/2+ΔVideal 
When Rdata=RH:
VSA_data=Vdata_1st_ideal+VSC_OS1 
VSA_REF=Vref_2nd_ideal+VSC_OS1 
VSA_data−VSA_REF=2ΔVideal 
where Vdata_1st_ideal 
=(Vdata0_ideal+Vdata1_ideal)/2+ΔVideal 
Vref_2nd_ideal 
=(Vdata0_ideal+Vdata1_ideal)/2−ΔVideal 
Note that the offset voltage (VSC_OS) in the sensing circuit is canceled out.
In addition, conventional offset tolerant sensing circuits use an irregular array structure. FIGS. 1C and 1D illustrates examples of a conventional offset tolerant sensing circuit in an irregular array structure. In FIG. 1C, a conventional offset tolerant sensing circuits in an irregular array structure uses two single pass transistor and double MTJs for Rref generation (two 1T2MTJs). The irregular array structure using two 1T2MTJs has the following problems in the reference cell: regularity problem because the reference cell requires a 1T2MTJ cell that is different from the 1T1MTJ data cell; write current degradation because of the serially connected RL and RH reference cells; and area overhead because of the inherent characteristics of the reference bit line (Ref-BL) structure: the number of word lines (WLs, e.g. 512) is much greater than the number of bit lines (BLs, e.g. 16) corresponding to an sense amplifier (SA).
In FIG. 1D, a conventional offset tolerant sensing circuits in an irregular array structure uses four single pass transistor and single MTJ for Rref generation (four 1T1MTJs). The irregular array structure using four 1T1MTJs has the following problems in the reference cell: control signal complexity because only one reference cell is used for every four BLs; and area overhead due to the additional write driver. For effective offset-tolerant sensing, as shown, a conventional offset tolerant sensing circuit in an irregular array structure may cause a regularity problem, additional cost, and design complexity over the previous offset tolerant sensing scheme.
Thus, an offset tolerant sensing scheme with a regular array structure is needed that does not have a regularity problem, additional costs, and design difficulty. Accordingly, there is a need for systems, apparatus, and methods that improve upon conventional approaches including the improved methods, systems, and apparatus provided hereby for removing the effect of offset voltages in correctly sensing or reading the bit cells of a MTJ array without requiring “irregular” structures like specially created reference cells, whose structure is different from the structure of the data cells.